Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits View on Open Library

Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits

by David M. Russinoff

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First published: 1995 1 language
Subjects
Hardware description languages VHSIC (Circuits) Mathematical models Program verification (Computers) Protocol (Computers)

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